A generally known CT detector has a number of hardware components with field-programmable gate arrays (=FPGAs). During operation a very wide variety of information (register contents) of the FPGAs must be written, read and evaluated by an external central control. This central control possesses only one communication link to the CT detector. For this reason internal connection paths between the FPGAs must be created in the CT detector, via which the central control can access all registers at any time. The central control in such cases requires a fixed reaction time of the CT detector. Since the internal connections for register accesses to the individual FPGAs are of different lengths and to some extent no direct access to the corresponding registers is possible, the reaction time also varies for different registers depending on their hierarchy level. In some cases the maximum reaction time demanded by the central control cannot be adhered to.
The data is transmitted between two hierarchy levels in such cases in accordance with the general timing behavior of a CT detector, by “readings”. This means that, to overcome each hierarchy level, the duration of a reading (integration and readout time of the radiation measuring detector elements) is needed. In order to reach registers of hierarchically remote FPGAs, a corresponding multiple of the reading time is thus needed.
In parallel thereto there are internal control sequences in the CT detector which likewise simultaneously evaluate register contents from other FPGAs. For this purpose current register values of all FPGAs must always be available centrally and directly. A further requirement is the synchronous setting of a register in a number of HW components operating in parallel. This “broadcast” access from the central control should be made possible using only one register access.
In the known CT detectors, the central control must thus issue a number of update commands before the content of the desired register can then be accessed, possibly over a number of hierarchy levels below, and can be transmitted back until it is available. Access to all registers in the CT detector is thus only tedious and slow using this concept. Furthermore this procedure is very prone to errors, since for internal control sequences the individual register values have been inserted into the existing data transmission paths in order to rapidly and synchronously reach the register contents needed.
A direct access to FPGAs lying remotely in the hierarchy is not possible with prior-art detectors. Access must be initiated here in a complicated manner via a register set. This fact significantly reduces the bandwidth for accesses to such FPGAs. It also complicates the activation because ever more accesses are needed here until a register can be written or read respectively. Write or read accesses of the central control should however be able to be processed immediately.